This invention relates to memory cells. More particularly, the present invention relates to nanometer-scale memory cells that utilize nanotubes, or other nanometer-scale filaments, as a charge sensing mechanism.
Writing and erasing a charge into a charge containment layer is well known in the art. Moreover, multiple distinct charges can now be stored in separate portions of a single containment layer. Examples of such memory cells can be found, for example, in U.S. Pat. Nos. 5,768,192 and 6,011,725. However, current systems utilize transistors to determine if a charge is stored in a containment layer.
More particularly, current systems position a charge containment layer between the channel and gate of a transistor such as a metal oxide field-effect transistor (MOSFET). If a charge is stored in this charge containment layer then the turn-ON voltage of the transistor increases. In this manner, a charge is determined as being stored by applying different turn-ON voltages and determining for which turn-ON voltage the transistor turns ON. Correlating (mapping) the turn-ON voltage to a bit (e.g., a 1 if a charge is stored or a 0 if a charge is not stored) provides the functionality of a base-two memory cell; the functionality of being able to store two information states (ON and OFF) in a memory cell.
MOSFETs are deficient because they have minimum sizing limitations that generally reside in the micrometer scale. It is therefore desirable to provide a memory cell that is sized on the nanometer-scale. It is also desirable to provide nanometer-scale memory cells that can be utilized to store several bits of information, several states of information, or store a bit of information having several states (e.g., can provide a base-three or base-four information bit). It is also desirable to provide memory cells that consume low amounts of power and can store very small levels of charge.